1. Field of the Invention
The present invention relates to an electrically rewritable nonvolatile semiconductor device and, more particularly, to a nonvolatile semiconductor memory device which has NAND cell units and in which plural select gate voltages are applied to select gate transistors during writing operation.
2. Description of the Related Art
An EEPROM in which data can be electrically rewritten is known as a nonvolatile semiconductor memory. Normally, floating gates acting as a charge storage layer and control gate stacked MOS transistors are used as memory cells in an EEPROM.
A NAND flash memory is known as a memory most adapted for providing increased capacity among EEPROMs. In the NAND flash memory, NAND cell units connected in series with each other are formed. In particular, adjacent ones of the memory cells share a source/drain diffusion layer. One end of each NAND cell unit is connected with a common source line via a first select gate transistor. The other end is connected with bit lines via a second select gate transistor. These NAND cell units share word lines and the select gates of select gate transistors to form a NAND cell array, the word lines being the control gates of memory cells.
In this NAND flash memory, 0 level (0 V) or 1 level (power voltage Vdd) is applied to each bit line according to writing data during writing of data. A given voltage VSOURCE is given to the common source line. A gate voltage of Vss is applied to the first select gate transistor. A gate voltage of VSG (=Vdd) is applied to the second select gate transistor. This turns off the first select gate transistor. The second select gate transistor is turned on. Consequently, 0 V is transferred to the channels of the NAND cell units including memory cells into which “0” is written. The channels of the NAND cell units including memory cells that are not written (i.e., maintained at “1”) are electrically charged to Vdd-Vth, where Vth is the threshold value of the second select gate transistor. The second select gate transistor is turned off. The channels in the units are floated. Subsequently, a programming voltage of about 20 V is applied to word lines with which memory cells to be written are connected. A pass voltage of about 10 V is applied to word lines with which the other memory cells are connected. As a result, in the NAND cell units into which “0” is to be written, a high voltage is applied to the floating gates of the memory cells to be written. Electrons are injected from the substrate side via a tunnel oxide film. In consequence, the threshold value of the memory cells shifts in the positive direction, thus completing the writing. Meanwhile, in the NAND cell units not written, the channels are in floating state. Therefore, capacitive coupling between the control gate and the semiconductor substrate boosts the channels, inhibiting writing into the memory cells.
In the NAND cell unit not written in this way, it is necessary that the first and second select gate transistors be kept off. In practice, however, a slight amount of leakage current may be produced through the select gate transistors. Therefore, the channel voltage rises to Vdd-Vth. After the second select gate transistor has been turned off, in order to minimize the leakage current through the second select gate transistor, the gate voltage of the second select gate transistor is set to a second select gate voltage VSGD that is lower than the first select gate voltage VSG of about 4 V. However, if the second select gate voltage VSGD is lowered excessively, the select gate transistors of NAND cell units into which “0” will be written are also turned off. Therefore, it is impossible to reduce the voltage below the threshold voltage of the select gate transistors. Especially, where quick pass write (QPW) is implemented when data is written in order to control the distribution of threshold values to a narrow range, using a multi-valued memory, it is required that a bit voltage VBL_QPW of about 0.5 to 0.7 V be applied to the bit lines connected to the NAND cell units into which “0” is written and that the bit voltage be transferred to the channel in the second stage of the writing process. For this reason, the second select gate voltage VSGD is set to an appropriate value within a range of 1.2 to 3.6 V in the manufacturing stage of the device.
In this way, the second select gate voltage VSGD of 1.2 to 3.6 V is applied to the select gates on the bit line side during writing subsequently to the first select gate voltage VSG of about 4 V. When the select gate voltage is switched between the first select gate voltage VSG and the second select gate voltage VSGD, a period in which the select gates are discharged and a period in which the select gates are charged are necessary. It is assumed, for example, that the second select gate voltage VSGD is 2.5 V. If the periods are set to optimum values under this condition, it is likely that the target voltage is not reached even through the same period provided that the second select gate voltage VSGD is 1.2 V or 3.6 V. One conceivable solution to this problem is to set the period for which charging is done by the second select gate voltage VSGD to a sufficiently long time. In this case, there is the problem that the writing time is prolonged.